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ST10F166
16-BIT MCU WITH 256K FLASH MEMORY
s
s
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s s
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s s
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s s s s
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s s
High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 x 16 bit), 1 s Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Up to 256 KBytes Linear Address Space for Code and Data 1 KByte On-Chip RAM 32 KBytes On-Chip Flash EPROM with Bank Erase Feature Protection-Optional Flash Memory Dedicated Flash Control Register with Operation Lock Mechanism 12 V External Flash Programming Voltage Flash Program Verify and Erase Verify Modes 1000 Flash Program/Erase Cycles guaranteed Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/ Data Buses Hold and Hold-Acknowledge Bus Arbitration Support 512 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)
PQFP100
s s
s s
s s s s
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16-Priority-Level Interrupt System 10-Channel 10-bit A/D Converter with 9.7 s Conversion Time (ST10F166) 16-Channel Capture/Compare Unit Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (USARTs) Programmable Watchdog Timer Up to 76 General Purpose I/O Lines Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 100-Pin Plastic PQFP Package
February 1996
This is preliminary information from SGS-THOMSON. Details are subject to change without notice.
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Table of Contents
Page Number
ST10F166 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 EXTERNAL BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 FLASH MEMORY PROGRAMMING AND ERASURE . . . . . . . . . . . . . . . . . 12 6 FLASH MEMORY SECURITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CENTRAL PROCESSING UNIT (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 A/D CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SERIAL CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 15 17 20 21
11 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12 PARALLEL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 13 14 15 16 17 CAPTURE/COMPARE UNIT (CAPCOM) . . . . . . . . . . . . . . . . . . . . . . . . . . GENERAL PURPOSE TIMER (GPT) UNIT . . . . . . . . . . . . . . . . . . . . . . . . SOFTWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPECIAL FUNCTION REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . . . . 23 25 28 31 33
18 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18.2 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18.4 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18.5 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 18.6 Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 18.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 19 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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ST10F166
1 INTRODUCTION
The ST10F166 is the FLASH memory members of the ST10 family of microcontrollers developed and produced by SGS-THOMSON Microelectronics in CMOS technology. they combine high CPU performance (up to 10 million instructions per second) with high peripheral functionality, enhanced IO-capabilities and an on-chip reprogrammable 32 KByte Flash Memory. The ST10F166-16 derives its CPU clock signal (operating clock) directly from the onchip oscillator without using a prescaler. With a clock duty cycle of 0.4 to 0.6, the recommended clock frequency is 16MHz for the ST10F166. The ST10F166 operates at half the oscillator clock frequency (using a 2:1 oscillator prescaler). Figure 1. Logic Symbol
VDD
VSS
Port 0 = 16-Bit
Port 1 = 16-Bit
Port 2 = 16-Bit
ST10F160 / F166
Port 3 = 16-Bit
Port 4 = 2-Bit
VPP/EBC1
Port 5 = 10-Bit
VR02058
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ST10F166
Figure 2. Pin Configuration Rectangular PQFP-100 (top view)
VSS VDD
VDD VS S
VSS VDD
ST10F160 / ST10F166
VDD VDD VSS
VS S
VPP / EBC1
VDD VSS
VR02056
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ST10F166
Table 1. Pin Definition and Function
Symbol Pin Input (I) Number Output (O) 16 - 17 I/O Function Port 4 is a 2-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0A16Least Significant Segment Addr. Line P4.1A17Most Significant Segment Addr. Line XTAL1:Input to the oscillator amplifier and input to the internal clock generator XTAL2:Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. External Bus Configuration selection inputs. These pins are sampled during reset and select either the single chip mode or one of the four external bus configurations: BUSACTEBC1EBC0Mode/Bus Configuration 00 0 8-bit demultiplexed bus 00 1 8-bit multiplexed bus 01 0 16-bit muliplexed bus 01 1 16-bit demultiplexed bus 10 0 Single chip mode 10 1 Reserved. 11 0 Reserved. 11 1 Reserved. After reset pin EBC1 accepts the programming voltage for the Flash Memory as an "alternate function": Flash Memory Programming Voltage V PP = 12 V. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10R165. An internal pullup resistor permits power-on reset using only a capacitor connected to V SS. Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed.
P4.0 - P4.1 16 17 O O
XTAL1 XTAL2
20 19
I O
BUSACT,
EBC1, EBC0
22 23 24
I I I
VPP
RSTIN
23 27 I
RSTOUT
28
O
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ST10F166
Table 1. Pin Definition and Function
Symbol Pin Input (I) Number Output (O) Function Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10R165 to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pull NMI high externally. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Memory Read Strobe. RD is activated for every external instruction or data read access. Port 1 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.. Port 5 is a 10-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 10) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x) for ST10F166 & ST10F166-16. Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The following Port 2 pins also serve for alternate functions: P2.0CC0IOCAPCOM: CC0 Cap.-In/Comp.Out ... ... ... P2.13CC13IOCAPCOM: CC13 Cap.-In/Comp.Out, BREQExternal Bus Request Output P2.14CC14IOCAPCOM: CC14 Cap.-In/Comp.Out, HLDAExternal Bus Hold Acknowl. Output P2.15CC15IOCAPCOM: CC15 Cap.-In/Comp.Out, HOLDExternal Bus Hold Request Input
NMI
29
I
ALE RD
25 26
O O
P1.0 - P1.15
30 - 37 40 - 47
I/O
P5.0 - P5.9
48 - 53 56 - 59 62 - 77
I I I/O
P2.0 - P2.15
62 ... 75 76 77
I/O I/O O I/O O I/O I
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ST10F166
Table 1. Pin Definition and Function
Symbol Pin Input (I) Number Output (O) I/O 80 - 92, I/O 95 - 97 Function Port 3 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The following Port 3 pins also serve for alternate functions: P3.0T0INCAPCOM Timer T0 Count Input P3.1T6OUTGPT2 Timer T6 Toggle Latch Output P3.2CAPINGPT2 Register CAPREL Capture Input P3.3T3OUTGPT1 Timer T3 Toggle Latch Output P3.4T3EUDGPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5T4INGPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6T3INGPT1 Timer T3 Count/Gate Input P3.7T2INGPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8TxD1ASC1 Clock/Data Output (Asyn./Syn.) P3.9RxD1ASC1 Data Input (Asyn.) or I/O (Syn.) P3.10TxD0ASC0 Clock/Data Output (Asyn./Syn.) P3.11RxD0ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12BHEExt. Memory High Byte Enable Signal, P3.13WRExternal Memory Write Strobe P3.14READYReady Signal Input P3.15CLKOUTSystem Clock Output (=CPU Clock) Port 0 is a 16-bit bidirectional IO port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width:8-bit 16-bit P0.0 - P0.7:D0 - D7 D0 - D7 P0.8 - P0.15:output! D8 - D15 Multiplexed bus modes: Data Path Width:8-bit 16-bit P0.0 - P0.7:AD0 - AD7AD0 - AD7 P0.8 - P0.15:A8 - A15 AD8 - AD15 Reference voltage for the A/D converter for ST10F166 & ST10F166-16.. Reference ground for the A/D converter for ST10F166 & ST10F166-16.. Digital Supply Voltage: + 5 V during normal operation and idle mode. 2.5 V during power down mode Digital Ground.
P3.0 - P3.15
80 81 82 83 84 85 86 87 88 89 90 91 92 95 96 97
I O I O I I I I O I/O O I/O O O I O
P0.0 - P0.15
98 - 5 8 - 15
I/O
VAREF VAGND VDD
54 55 7, 18, 38, 61, 79, 93 6, 21, 39, 60, 78, 94
-
VSS
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-
ST10F166
2 MEMORY ORGANIZATION
The memory space of the ST10F166 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which currently includes 256 Kbytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The ST10F166 contains 32 Kbytes of FLASH EPROM for code or constant data, mapped in segment 0 or in segment 1 by software. A large dual port RAM of 1 Kbyte is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, . . ., RL7, RH7) called General Purpose Registers (GPRs). 512 bytes of the address space are reserved for the Special Function Register (SFR) area. SFRs are registers which are used for controlling and monitoring functions of the different on-chip units. 118 SFRs are currently implemented. Unused SFR addresses are reserved for future members of the ST10 Family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 256 Kbytes of external RAM and/or ROM can be connected to the microcontroller.
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ST10F166
3 EXTERNAL BUS CONTROLLER
All external memory accesses are performed by the on-chip External Bus Controller (EBC). During Reset, it can be programmed to either the Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follow: 16/18 bit Addresses, 8 bit Data, Demultiplexed 16/18 bit Addresses, 8 bit Data, Multiplexed 16/18 bit Addresses, 16 bit Data, Demultiplexed 16/18 bit Addresses, 16 bit Data, Multiplexed In the demultiplexed bus mode, Port 1 is used as an output for addresses and Port 0 is used as an input/output for data. In the multiplexed bus modes, one of the two 16 bit ports, Port 0, is used as an input/output for both addresses and data. For applications which require less than 64 Kbytes of memory space, a non-segmented memory model can be selected. During the initialization phase, the bus configuration and mapping of the Flash Memory to segment 1 may be programmed. After the EINIT instruction, only the external bus configuration can be changed at any time. In this case,all memory locations can be addressed by 16 bits, and thus port 4 is not needed as an output for the two significant address biss (A17 and A16, as is the case when using the segmented memory model.
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0FFFFh 0FFE0h
0FFDFh 3FFFFh
0FF00h
512 Bytes Internal SFRs 2FFFFh
Figure 3. Memory Organization
0FE00h 32 KBytes External Memory 0FFFFh 1FFFFh
PEC Source and 0FDFFh Destination Pointers 0FDE0h
64 KBytes External Memory
Internal Memory 31,5 KBytes External Memory
0FD00h
64 KBytes External Memory 30000h Code Segement 3
Context Pointer
GPRs
Stack Pointer 07FFFh
32 KBytes 17FFFh External Memoryl or
20000h Code Segment 2
0FBFFh
System Stack
32 KBytes Internal Internal FLASH FLASH Memory Memory or External Memory
10000h Code Segment 1
1 Kbyte Internal RAM
0FA00h 00000h Bit Addressable space
Code Segment 0
ST10F166
INTERNAL MEMORY
INTERNAL/EXTERNAL MEMORY
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ST10F166
4 FLASH MEMORY
The ST10F166 provides, in addition to the RAM, 32 k bytes of Electrically Erasable and reprogram-mable non-volatile (FLASH) memory. This memory is organised as 8K x 32 bit allowing a complete instruction to be read during one instruction fetch cycle. Data values stored can be read as 16 bit operands using all addressing modes of ST10F166 instruction set. The FLASH memory is located in segment 0 (0 to 07FFFh) during reset, and thus contains the reset and interrupt vectors. To provide full flexibility in the use of the ST10F166, the FLASH memory may be remapped to segment ~ ( 0000 to 17FFFh) during initialization. This allows the interrupt vector to be programmed from external memory, while retaining the common routines and constants programmed into the FLASH memory. For ease of program updating, the FLASH memory is organised into 4 banks, each of which may be independently Erased. Table 2. FLASH memory Bank Organisation
Bank 0 1 2 3 Addresses (Segment 0) 00000h to 02FFFh 03000h to 05FFFh 06000h to 077FFh 07800h to 07FFFh Size (bytes) 12K 12K 6K 2K
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ST10F166
5 FLASH MEMORY PROGRAMMING AND ERASURE
The FLASH memory is programmed using the PRESTO F Program Write algorithm for reliability. This algorithm provides a typical programming time of 25s per word and erasing of 1s per bank. Erasure of the FLASH memory is performed in the program mode using the PRESTO F Erase algo-rithm, and operates on the selected bank of the memory. Timing of the Write/Erase cycles is automatically generated by a programmable timer and completion is indicated by a flag. A second flag indicates that the VPP voltage was correct for the whole programming cycle to ensure reliability. The FLASH memory features a typical endurance of 100 Erase/Program cycles.
6 FLASH MEMORY SECURITY
Security and reliability are enhanced by the built-in features. A key code sequence is used to enter the Write/Erase mode preventing false write cycles, while a programmable option (set by the programming board) prevent any access to the FLASH memory from the internal RAM or from External Memory. If the security option is set, the FLASH memory is accessed only from program within the FLASH memory area. This protection may be disabled by instructions executed from the FLASH memory only (when not in write/erase mode).
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ST10F166
Figure 4. PRESTO F Program Write Algorithm
=0
PCOUNT=PNmax?
PCOUNT=PCOUNT+1
VR02057A
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ST10F166
Figure 5. PRESTO F Erase Algorithm
=0
PCOUNT=ENmax?
PCOUNT=PCOUNT+1
VR02057B
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ST10F166
7 CENTRAL PROCESSING UNIT (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware provide a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the ST10F166 instructions can be executed in just one machine cycle which requires 100 ns at 20 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. For fast execution: All multiple-cycle instructions have been optimized . A 32-/16 bit division in 1 s, a 16 x 16 bit multiplication in 0.5 s, and program branches in 200 ns. Another pipeline optimization, the 'Jump Cache', allows reducing the execution time of repeatedly performed jumps in a loop from 200 ns to 100 ns. The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at the time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, register banks can also be organized to overlapping. A system stack of up to 512 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.
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ST10F166
C.P.U. (Cont'd)
The high performance offered by the hardware implementation of the CPU can efficiently be used by a programmer via the highly functional ST10F166 instruction set which includes the following instruction classes: - Arithmetic Instructions - Logical Instructions - Boolean Bit Manipulation Instructions - Compare and Loop Control Instructions - Shift and Rotate Instructions - Prioritize Instruction - Data Movement Instructions - System Stack Instructions - Jump and Call Instructions - Return Instructions - System Control Instructions - Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands Figure 6. CPU Block Diagram
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ST10F166
8 INTERRUPT SYSTEM
With an interrupt response time within a range from 250 ns to 500 ns (in case of internal program execution), the ST10F166 is capable of reacting very fast to the occurance of non-deterministic events. The architecture of the ST10F166 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is 'stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an optional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when operating in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corres-ponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data, or for transferring A/D converted results to a memory table. The ST10F166 has 8 PEC chan-nels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit field exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Software interrupts are supported by means of the 'TRAP' instruction in combination with an individual trap (interrupt) number. The ST10F166 also provides an efficient mechanism to identify and to process 'HardwareTraps' exceptions or error conditions that arise during run-time. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
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ST10F166
Interrupt System (Cont'd)
The following table shows all of the possible ST10F166 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 3. Interrupt Sources and Hardware Location
Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Timer 0 CAPCOM Timer 1 GPT 1 Timer 2 GPT 1 Timer 3 GPT 1 Timer 4 GPT 1 Timer 5 GPT 1 Timer 6 GPT 2 CAPREL Register A/D Conversion Complete A/D Overrun Error Serial Channel 0 Transmit Serial Channel 0 Receive Serial Channel 0 Error Serial Channel 1 Transmit Serial Channel 1 Receive Serial Channel 1 Error Request Flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR T0IR T1IR T2IR T3IR T4IR T5IR T6IR CRIR ADCIR ADEIR S0TIR S0RIR S0EIR S1TIR S1RIR S1EIR Enable Flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE T0IE T1IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0RIE S0EIE S1TIE S1RIE S1EIE Interrupt Vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT T0INT T1INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0RINT S0EINT S1TINT S1RINT S1EINT Vector Location 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh Trap Number 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh
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ST10F166
Interrupt System (Cont'd)
Except when another higher prioritized trap service being in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run-time: Table 4. Exceptions and Errors during Runtime
Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 28h 28h 28h 28h 28h [2Ch - 3Ch] Ah Ah Ah Ah Ah [Bh - Fh] Current CPU Priority I I I I I NMI STKOF STKUF RESET RESET RESET NMITRAP STOPTRAP STUTRAP 0h 0h 0h 0h 0h 0h III III III Trap Flag Trap Vector Vector Location Trap Number Trap priority
08h 10h 18h
2h 4h 6h
II II II
Software Traps TRAP Instruction
Any [0h - 1FCh] in steps of 4h
Any [0h - 7Fh]
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ST10F166
9 A/D CONVERTER
For analog signal measurement, a 10-bit A/D converter with 10 multiplexed input channels, a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation which returns the conversion result for an analog channel within 9.75 s (@fosc = 40 MHz). Overrun error detection capability is provided for the conversion result register (ADDAT): an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete. For applications which require less than 10 analog input channels, the remaining channels can be used as digital input port pins. The A/D converter of the ST10F166 supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is once sampled and converted into a digital result. In the Single Channel Continuous mode, the analog level is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer.
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ST10F166
10 SERIAL CHANNELS
Serial communication with other microcontrollers, processors, terminals, or external peripheral components is provided by two serial interfaces with identical functionality, Serial Channel 0 (ASC0) and Serial Channel 1 (ASC1). They support full-duplex asynchronous communication up to 625 Kbaud and half-duplex synchronous communication up to 2.5 Mbaud. Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel. In the synchronous mode, one data byte is transmitted or received synchronously to a shift clock which is generated by the ST10F166. In the asynchronous mode, an 8or 9-bit data frame is transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode), and a loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete.
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ST10F166
11 WATCHDOG TIMER
The Watchdog Timer of the ST10F166 represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer of the ST10F166 is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. When the software has been designed to service the Watchdog Timer before it overflows, the Watchdog Timer times out if the program does not progress properly due to hardware or software related failures. When the Watchdog Timer overflows, it generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to reset. The Watchdog Timer of the ST10F166 is a 16-bit timer which can either be clocked with fosc/4 or fosc/256. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 s and 420 ms can be monitored (@fosc = 40 MHz). The default Watch-dog Timer interval after reset is 6.55 ms.
12 PARALLEL PORTS
The ST10F166 provides 76 I/O lines which are organized into four 16-bit I/O ports (Port 0 through 3), one 2-bit I/O port (Port 4), and one 10-bit input port (Port 5). All port lines are bit addressable, and all lines of Port 0 through 4 are individually bit programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to the high impedance state when configured as inputs. During the internal reset, all port pins are configured as inputs. Each port line has one programmable alternate input or output function associated with it. Ports 0 and 1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A16 and A17 in systems where segmentation is enabled to access more than 64 Kbytes of memory. Port 2 is associated with the capture inputs/compare outputs of the CAPCOM unit, and Port 3 includes alternate functions of timers, serial interfaces, optional bus control signals (WR, BHE, READY), and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter. When none of the alternate functions is not used, the respective port line may be used as general purpose I/O line.
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ST10F166
13 CAPTURE/COMPARE UNIT (CAPCOM)
The CAPCOM unit supports generation and control of timing sequences on up to 16 channels, with a maximum resolution of 400 ns. The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PWM), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T0/T1) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustment to the application specific requirements. In addition, an external count input for CAPCOM timer T0 allows event scheduling for the capture/compare registers relative to external events. The capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1, and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched ('captured') into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode.
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CAPCOM (Cont'd)
Table 5. Compare Modes
Compare Modes Mode 0 Mode 1 Mode 2 Mode 3 Double Register Mode Functions Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated Pin set to '1' on match; pin reset to '0' on compare timer overflow; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.
Figure 7. CAPCOM Block Diagram
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ST10F166
14 GENERAL PURPOSE TIMER (GPT) UNIT
The GPT unit represents a very flexible multifunctional timer counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the internal system clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the 'gate' level on an external input pin. For these purposes, each timer has one associated port pin (T2IN, T3IN, T4IN) which serves as gate or clock input. The maximum resolution of the timers in the GPT1 module is 400 ns (@fosc = 40 MHz). The count direction (up/down) for each timer is programmable by software. For timer T3, the count direction may additionally be altered dynamically by an external signal on a port pin (T3EUD) to facilitate functions such as position tracking. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on a port pin (T3OUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.
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G.P.T. (Cont'd)
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins (T2IN, T4IN). Timer T3 is reloaded with the contents of T2 or T4 either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. With its maximum resolution of 200 ns (@fosc = 40 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can independently count up or down, clocked with an input clock which is derived from a programmable prescaler. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the same signal transition. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead.
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G.P.T. (Cont'd)
Figure 8. GPT1 Block Diagram
System Clock (fosc2) T2in-P3.7
/2n n=3...10
GPT1 Timer T2 T2 Mode Reload U/D Control Capture
Interrupt Request
System Clock (fosc2) T3in-P3.6 T3Eud-P3.4
/2n n=3...10
T3 Mode Control
GPT1 Timer T3 U/D Capture
T3OTL Toggle FF
T3out-P3.3
T4in-P3.5 System Clock (fosc2)
/2n n=3...10
T4 Reload Mode Control GPT1 Timer T4 U/D
VR02074A
Interrupt Request
Figure 9. GPT2 Block Diagram
System Clock (fosc2)
/2n n=2...9
Input Control
GPT2 Timer T5 Clear U/D
Interrupt Request
CAPin-P3.2
Interrupt Request GPT2 CAPREL Interrupt Request
To CAPCOM Timers T0,T1
System Clock (fosc2)
/2n n=2...9
GPT2 Timer T6 U/D
T6OTL Toggle FF
T6out-P3.1
VR02074B
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ST10F166
15 SOFTWARE DESCRIPTION
Addressing Modes The ST10F166 offers different powerful addressing modes to facilitate rapid access on word, byte and bit data, or to specify the destination address of a branch instruction. The addressing modes are subdivided in six different categories as follows. Short addressing modes: an implicit base offset address is used to specify a physical 18-bit address. EA = Base Address + k Short Address. k = 1 or 2 EA = Effective Address This mode allows direct access to any GPR or SFR and any word in the bit-addressable memory space. (in case of a byte operation on an SFR, only the low byte can be accessed via `reg'). Long addressing modes: one of the four DPP registers, selected by bit 15 and 14 of the 16-bit address, is used to specify a physical 18-bit address. EA = Contents of DPPi + Page Offset Address i: specified by bit 15, 14 of the 16 bit address. Page Offset Address: bit 13 to 0 of the 16 bit address. In this mode, any word or byte data within the entire memory space can be accessed directly . Word accesses may not be performed on odd byte addresses, otherwise a hardware trap will occur. Indirect addressing modes: a 16-bit long address is specified indirectly by the contents of a word GPR which is specified directly by a short address. Any word GPR can be used, except for arithmetic, logical and compare instructions, where only R0 to R3 are allowed. There are also certain modes which allow decrementing or incrementing the indirect address pointers by a data-type-dependent value. Long Address = [GPR Address] + Constant EA = Contents of DPPi + Page Offset Address i: specified by bit 15, 14 of the Long Address. Page Offset Address: bit 13 to 0 of the long address Long Address Long Address bit15,14 specify i bit 13 to 0
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Immediate data: these data are represented in the instruction formats by either 3,4,8 or 16 bits. Branch target addressing modes: to specify the destination address and segment of jump or call instructions, relative, absolute and indirect modes can be used to update the Instruction Pointer (IP) register while the Code Segment Pointer (CSP) register can be updated only with absolute values. Condition Flags: The condition flags of the PSW register (N,C,V,Z,E) indicate the ALU status due to the last performed ALU operation. They are set by most of the instructions due to specific rules which depend on the ALU or data movement operation performed by an instruction. If the PSW register is the destination operand of an instruction, the PSW flags do NOT represent the condition flags of this instruction as usual. E: End of a table in a table search operation Z: Zero V: Overflow C: Carry N: Negative
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Software Description (Cont'd)
Table 6. Addressing Mode Summary
Addressing Mode 3 bit Immediate Data 4 bit Immediate Data 8 bit Immediate Data 16 bit Immediate Data 8 bit Immediate Mask GPR register direct SFR or GPR register direct Memory direct Memory indirect Memory indirect with Post-increment Memory indirect with Pre-decrement Memory indirect with a 16-bit cinstant Direct Word Offset Bit Address Notation #data3 #data4 #data8 #data16 #mask Rw reg Mem [Rw] [Rw+] [-Rw] [Rw+#data16] bitoff bitaddr.b Rb
Table 7. Condition Code Summary
UC Z NZ V NV N NN C NC EQ NE ULT UGE ULE UGT SLT SGE SLE SGT NET Unconditional Zero No Zero Overflow No Overflow Negative Not Negative Carry No Carry Equal Not Equal Unsigned Less Than Unsigned Greater Than or Equal Unsigned Less Than or Equal Unsigned Greater Than Signed Less Than Signed Greater Than or Equal Signed Less Than or Equal Signed Greater Than Not Equal AND Not End of Table 1=1 Z=1 Z=0 V=1 V=0 N=1 N=0 C=1 C=0 Z=1 Z=0 C=1 C=0 (Z or C)=1 (Z or C)=0 (N xor V)=1 (N xor V)=0 (Z or (N xor V))=1 (Z or (N xor V))=0 (Z or E)=0
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16 INSTRUCTION SET SUMMARY
The table below lists the instructions of the ST10F166 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "ST10 Programming Manual". This document also provides a detailed description of each instruction.
Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR MOV(B)
Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR Move word (byte) data
Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2 2/4
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Instruction Set Summary (Cont'd)
Mnemonic MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT NOP Description Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Null operation Bytes 2/4 2/4 4 4 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2
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17 SPECIAL FUNCTION REGISTER OVERVIEW
The following table lists all SFRs which are implemented in the ST10F166 in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Physical Address b b FF98h FFA0h FEA0h FE18h FF9Ah FF14h FE4Ah b b b b b b b b b FE80h FF78h FE82h FF7Ah FE84h FF7Ch FE86h FF7Eh FE88h FF80h FE8Ah FF82h FE8Ch FF84h FE8Eh FF86h FE90h FF88h 8-Bit Address CCh D0h 50h 0Ch CDh 8Ah 25h 40h BCh 41h BDh 42h BEh 43h BFh 44h C0h 45h C1h 46h C2h 47h C3h 48h C4h Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Name ADCIC ADCON ADDAT
Description A/D Converter End of Conversion Interrupt Control Register A/D Converter Control Register A/D Converter Result Register Address Select Register A/D Converter Overrun Error Interrupt Control Register Bus Configuration Register GPT2 Capture/Reload Register CAPCOM Register 0 CAPCOM Register 0 Interrupt Control Register CAPCOM Register 1 CAPCOM Register 1 Interrupt Control Register CAPCOM Register 2 CAPCOM Register 2 Interrupt Control Register CAPCOM Register 3 CAPCOM Register 3 Interrupt Control Register CAPCOM Register 4 CAPCOM Register 4 Interrupt Control Register CAPCOM Register 5 CAPCOM Register 5 Interrupt Control Register CAPCOM Register 6 CAPCOM Register 6 Interrupt Control Register CAPCOM Register 7 CAPCOM Register 7 Interrupt Control Register CAPCOM Register 8 CAPCOM Register 8 Interrupt Control Register
ADDRSEL1 ADEIC b
BUSCON1 b CAPREL CC0 CC0IC CC1 CC1IC CC2 CC2IC CC3 CC3IC CC4 CC4IC CC5 CC5IC CC6 CC6IC CC7 CC7IC CC8 CC8IC
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Special Function Register Overview (Cont'd)
Name CC9 CC9IC CC10 CC10IC CC11 CC11IC CC12 CC12IC CC13 CC13IC CC14 CC14IC CC15 CC15IC CCM0 CCM CCM2 CCM3 CP CRIC CSP DP0 DP1 DP2 DP3 DP4 DPP0 DPP1 DPP2 DPP3 MDC MDH MDL ONES P0 b b b b b b b b b b b b b b b b b b b Physical Address FE92h FF8Ah FE94h FF8Ch FE96h FF8Eh FE98h FF90h FE9Ah FF92h FE9Ch FF94h FE9Eh FF96h FF52h FF54h FF56h FF58h FE10h FF6Ah FE08h FF02h FF06h FFC2h FFC6h FF0Ah FE00h FE02h FE04h FE06h FF0Eh FE0Ch FE0Eh FF1Eh FF00h 8-Bit Address 49h C5h 4Ah C6h 4Bh C7h 4Ch C8h 4Dh C9h 4Eh CAh 4Fh CBh A9h AAh ABh ACh 08h B5h 04h 81h 83h E1h E3h 85h 00h 01h 02h 03h 87h 06h 07h 8Fh 80h Description CAPCOM Register 9 CAPCOM Register 9 Interrupt Control Register CAPCOM Register 10 CAPCOM Register 10 Interrupt Control Register CAPCOM Register 11 CAPCOM Register 11 Interrupt Control Register CAPCOM Register 12 CAPCOM Register 12 Interrupt Control Register CAPCOM Register 13 CAPCOM Register 13 Interrupt Control Register CAPCOM Register 14 CAPCOM Register 14 Interrupt Control Register CAPCOM Register 15 CAPCOM Register 15 Interrupt Control Register CAPCOM Mode Control Register 0 CAPCOM Mode Control Register 1 CAPCOM Mode Control Register 2 CAPCOM Mode Control Register 3 CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (2 bits, read only) Port 0 Direction Control Register Port 1 Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register (2 bits) CPU Data Page Pointer 0 Register (4 bits) CPU Data Page Pointer 1 Register (4 bits) CPU Data Page Pointer 2 Register (4 bits) CPU Data Page Pointer 3 Register (4 bits) CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Constand Value 1's Register (read only) Port 0 Register Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h FC00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0001h 0002h 0003h 0000h 0000h 0000h FFFFh 0000h
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Special Function Register Overview (Cont'd)
Name P1 P2 P3 P4 P5 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PSW S0BG S0CON S0EIC S0RBUF S0RIC S0TBUF S0TIC S1BG S1CON S1EIC S1RBUF S1RIC S1TBUF S1TIC SP STKOV STKUN SYSCON b T0 T01CON b b b b b b b b b b b b b b b Physical Address FF04h FFC0h FFC4h FF08h FFA2h FEC0h FEC2h FEC4h FEC6h FEC8h FECAh FECCh FECEh FF10h FEB4h FFB0h FF70h FEB2h FF6Eh FEB0h FF6Ch FEBCh FFB8h FF76h FEBAh FF74h FEB8h FF72h FE12h FE14h FE16h FF0Ch FE50h FF50h 8-Bit Address 82h E0h E2h 84h D1h 60h 61h 62h 63h 64h 65h 66h 67h 88h 5Ah D8h B8h 59 B7h 58h B6h 5Eh DCh BBh 5Dh BAh 5Ch B9h 09h 0Ah 0Bh 86h 28h A8h Port 1 Register Port 2 Register Port 3 Register Port 4 Register (2 bits) Port 5 Register (10 bits, read only) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PECChannel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Description Reset Value 0000h 0000h 0000h 0000h XXXXh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
CPU Program Status Word 0000h Serial Channel 0 Baud Rate Generator Reload Reg0000h ister Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Transmit Interrupt Control Register Serial Channel 1 Baud Rate Generator Reload Register Serial Channel 1 Control Register Serial Channel 1 Error Interrupt Control Register Serial Channel 1 Receive Buffer Register (read only) Serial Channel 1 Receive Interrupt Control Register Serial Channel 1 Transmit Buffer Register (write only) Serial Channel 1 Transmit Interrupt Control Register CPU System Stack Pointer Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CAPCOM Timer 0 Register CAPCOM Timer 0 and Timer 1 Control Register 0000h 0000h XXXXh 0000h 0000h 0000h 0000h 0000h 0000h XXXXh 0000h 0000h 0000h FC00h FA00h FC00h 0XX0h*) 0000h 0000h
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Special Function Register Overview (Cont'd)
Name T0IC T0REL T1 T1IC T1REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC TFR WDT b b b b b b b b b b b b b Physical Address FF9Ch FE54h FE52h FF9Eh FE56h FE40h FF40h FF60h FE42h FF42h FF62h FE44h FF44h FF64h FE46h FF46h FF66h FE48h FF48h FF68h FFACh FEAEh FFAEh FF1Ch 8-Bit Address CEh 2Ah 29h CFh 2Bh 20h A0h B0h 21h A1h B1h 22h A2h B2h 23h A3h B3h 24h A4h B4h D6h 57h D7h 8Eh Description CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register CAPCOM Timer 1 Interrupt Control Register CAPCOM Timer 1 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register Constant Value 0's Register (read only) Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
WDTCON ZEROS b
*) The system configuration is selected during reset.
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18 ELECTRICAL CHARACTERISTICS
18.1 Absolute Maximum Ratings
Ambient temperature under bias (T A): . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70 C Storage temperature (TST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65 to +125 C Voltage on VCC pins with respect to ground (VSS) . . . . . . . . . . . . . . . . . -0.5 to +6.5 V Voltage on any pin with respect to ground (VSS) . . . . . . . . . . . . . -0.3 to VCC +0.3 V Input current on any pin during overload condition . . . . . . . . . . . . . . -10 to +10 mA. Absolute sum of all input currents during overload condition . . . . . . . . . . . .100 mA. Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5 W Flash programming voltage (VPP). . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to + 13.5 V Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VCC or VIN37/62
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18.3 DC Characteristics VCC = 5 V 10 %; TA = 0 to +70 C
Parameter Input low voltage EBC1/V PP Input low voltage (all except EBC1/VPP) Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1 Output low voltage (Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) Output high voltage (Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage (all other outputs) Input leakage current (Port 5)
1)
VSS = 0 V; fCPU = 20 MHz for ST10F166/166-16
Symbol VIL1 VIL2 VIH VIH1 VIH2 VOL VOL1 VOH SR SR SR SR SR CC CC CC Limit Values min. - 0.3 - 0.5 0.2 VCC + 0.9 0.6 VCC 0.7 VCC - - 0.9 VCC 2.4 0.9 VCC 2.4 - - - 50 - -500 - 2100 - max. 0.2 VCC - 0.1 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.45 0.45 - - 5008) 18) 100 150 -40 - 150 - 20 Unit V V V V V V V V V V V nA A A k A A A A A Test Condition - - - - - IOL = 2.4 mA IOL1 = 1.6 mA IOH = - 500 A IOH = - 2.4 mA IOH = - 250 A IOH = - 1.6 mA 0 V < VIN < VCC 0 V < VIN < VCC 0 VPP VCC - VOUT = VOHmin VOUT = VOLmax VOUT = VOLmax VOUT = VOHmin 0 V < VIN < VCC
VOH1 CC IOZ1 IOZ2 IPPS CC CC CC
Input leakage current (all other) VPP leakage current EBC1/V PP
RSTIN pullup resistor
6) 5)
RRST CC IRH IRL
3) 4) 3) 4)
Read inactive current Read active current ALE inactive current ALE active current
5) 5)
5)
IALEL IALEH IIL
XTAL1 input current
CC
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DC Characteristics (Cont'd)
Parameter Pin capacitance 6) (digital inputs/outputs) Power supply current Idle mode supply current Power-down mode supply current VPP read current
6)
Symbol CIO ICC IID IPD IPPR CC
Limit Values min. - - - TBD - max. 10 80 + 5 * f CPU 35 + 1.5 * fCPU TBD 200
Unit pF mA mA A A
Test Condition f = 1 MHz TA = 25 C RSTIN = VIL2 fCPU in [MHz] RSTIN = VIH1 fCPU in [MHz] - VPP > VCC 1/TCL = 40 MHz 32-bit programming VPP = 12 V
7)
7)
VPP write current 6)
IPPW
-
50
mA
VPP during write/read
VPP
11.4
12.6
V
Notes:
1) 3) 4) 5) 6) 7)
This specification does not apply to the analog input (Port 5.x) which is currently converted. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is only valid during Reset, or during Hold-mode. Not 100% tested, guaranteed by design characterization. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at V CCmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. This value is guaranteed also after ESD qualification trials at 25 degrees
8)
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DC Characteristics (Cont'd)
Figure 10. Supply/Idle Current as a Function of Operating Frequency
Current (mA)
250 ICC 200 Iid
150
100
50
0 0 5 10 CPU Frequency (MHz) 15
VR02049
20
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ST10F166
18.4 A/D Converter Characteristics VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C for ST10F166/166-16 4.0 V VAREF VCC+0.1 V; VSS-0.1 V VAGND VSS+0.2 V
Parameter Analog input voltage range Sample time Conversion time Total unadjusted error Internal resistance of reference voltage source 7) Internal resistance of analog source 7) ADC input capacitance 7) VAREF Supply Current
Notes:
1)
Symbol VAIN tS tC SR CC CC
Limit Values min. max. VAGND - - - - - - - VAREF 2 tSC 10 tCC + tS + 4TCL 3 tCC / 250 - 0.25 tS / 500 - 0.25 50 5
Unit V
Test Condition 1) 2) 4) 3) 4)
TUE CC RAREF CC RASRC CC CAIN IREF CC
LSB k k pF mA
5) tCC in [ns] 6) 7) tS in [ns] 2) 7) 7)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FF H, respectively. During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitors to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. The value for the sample clock is tSC = TCL * 32. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. The value for the conversion clock is tCC = TCL * 32. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. TUE is tested at VAREF=5.0V, VAGND=0V, VCC=4.8V. It is guaranteed by design characterization for all other voltages within the defined voltage range. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitors to reach their respective voltage level within tCC. The maximum internal resistance results from the CPU clock period. Not 100% tested, guaranteed by design characterization.
2)
3)
4) 5)
6)
7)
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ST10F166
18.5 Testing Waveforms Figure 11. Input Output Waveforms
AC inputs during testing are driven at 2.4 V for a logic `1' and 0.4 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
Figure 12. Float Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a100mV change from the loaded VOH/VOL leveloccurs (IOH/IOL = 20 mA).
18.6 Memory Cycle Variables The timing tables below use three variables which are derived from registers SYSCON and BUSCON1 and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed.
Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol tA tC tF Values TCL * 2TCL * (15 - ) 2TCL * (1 - )
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ST10F166
18.7 AC Characteristics The specification of the timings depends on the CPU clock signal that is used in the respective device. In this regard the specification for the ST10F166 and the ST10F166-16 are different. While the ST10F166-16 directly uses the clock signal fed to XTAL1 and therefore has to take into account the duty cycle variation of this signal, the ST10F166 derives its CPU clock from the XTAL1 signal via a 2:1 prescaler and therefore is independant from these variations. For these reasons the following pages provide the timing specifications for ST10F166 and for ST10F166-16 separately (where applicable). External Clock Drive XTAL1 for the ST10F166 VCC = 5 V 10 %; TA = 0 to +70 C
Parameter Oscillator period High time Low time Rise time Fall time
VSS = 0 V
Max. CPU Clock = 20 MHz min. 25 6 6 - - max. 25 - - 5 5 Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 25 6 6 - - max. 500 - - 5 5
Symbol TCL t1 t2 t3 t4 SR SR SR SR SR
Unit ns ns ns ns ns
Figure 13. External Clock Drive XTAL1
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ST10F166
AC Characteristics (Cont'd)
External Clock Drive XTAL1 for the ST10F166-16
VCC = 5 V 10 %;VSS = 0 V TA = 0 to +70 C Parameter Oscillator period High time Low time Rise time Fall time Oscillator duty cycle Clock cycle Symbol CLP TCLH TCLL tR tF DC TCL SR SR SR SR SR SR SR CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. max. 62.5 25 25 - - 0.4 25 62.5 - - 10 10 0.6 37.5 Variable CPU Clock 1/CLP = 1 to 20 MHz min. max. 50 25 25 - - 25 / CLP CLP * DCmin 1000 CLP-TCLL CLP-TCLH 10 10 1 - 25 / CLP CLP * DCmax Unit ns ns ns ns ns ns
Note: In order to run the ST10F166-16 at a CPU clock of 20 MHz the duty cycle of the oscillator clock must be 0.5, ie. the relation between the oscillator high and low phases must be 1:1. So the variation of the duty cycle of the oscillator clock limits the maximum operating speed of the device. The 16 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6.
Figure 14. External Clock Drive XTAL1
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ST10F166
AC Characteristics (Cont'd)
Multiplexed Bus for the ST10F166
VCC = 5 V 10 %;VSS = 0 V TA = 0 to +70 C CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates)
Max. CPU Clock = 20 MHz min. max. 15 + tA 10 + tA 15 + tA 15 + tA -10 + tA - - 40 + tC 65 + tC - - - - 0 - 35 + tC 35 + tF 35 + tF 35 + tF - - - - - 5 30 - - 30 + tC 55 + tC 55 + tA + tC 75 + 2tA + tC - 35 + tF - - - - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. TCL - 10 + tA TCL - 15 + tA TCL - 10 + tA TCL - 10 + tA -10 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - 2TCL - 15 + tC 2TCL - 15 + tF 2TCL - 15 + tF 2TCL - 15 + tF - - - - - 5 TCL + 5 - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 25 + 2tA + t C - 2TCL - 15 + tF - - - -
Parameter ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR
Symbol t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t22 t23 CC CC CC CC CC CC CC CC CC SR SR SR SR SR SR CC CC CC CC
Uni t ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ALE rising edge after RD, WR t25 Address hold after RD, WR t27
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ST10F166
AC Characteristics (Cont'd)
Multiplexed Bus for the ST10F166-16 VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C
CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates)
Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. max. 15 + t A 10 + t A 15 + t A 15 + t A -10 + tA - - 52.5 + tC 77.5 + tC - - - - 0 - 47.5 + tC 47.5 + t F 47.5 + t F 47.5 + t F - - - - - 5 42.5 - - 47.5 + tC 72.5 + tC 72.5 + tA + tC 100 + 2tA + tC - 47.5 + t F - - - - Variable CPU Clock 1/CLP = 1 to 20 MHz min. max. TCLmin - 10 + tA TCLmin - 15 + tA TCLmin - 10 + tA TCLmin - 10 + tA -10 + tA - - CLP - 10 + tC CLP+TCLmin - 10 + tC - - - - 0 - CLP - 15 + tC CLP - 15 + tF CLP - 15 + tF CLP - 15 + tF - - - - - 5 TCLmax + 5 - - CLP - 20 + tC CLP+TCLmin - 20 + tC CLP+TCLmin - 20 + tC 2CLP - 25 + 2tA + tC - CLP - 15 + tF - - - - Unit
ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR
t5 CC t6 CC t7 CC t8 CC t9 CC t10CC t11CC t12 CC t13 CC t14 SR t15 SR t16 SR t17 SR t18 SR t19 SR t22 CC t23 CC t25 CC t27 CC
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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ST10F166
AC Characteristics (Cont'd)
Figure 15. External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE
t5 ALE t16 t25
A17-A16 (A15-A8)
BHE
t17 Address t6 t7
t27
Read Cycle BUS Address t10 t14 t12
t19 t18 Data In
t8
RD
Write Cycle BUS Address t10
t23 Data Out
t8
WR
t22
t12
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ST10F166
AC Characteristics (Cont'd)
Figure 16. Ext. Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE
t5 ALE t16 t25
A17-A16 (A15-A8)
BHE
t17 Address t6 t7
t27
Read Cycle BUS Address t10 t14 t12
t19 t18 Data In
t8
RD
Write Cycle BUS Address t10 Data Out
t23
t8
WR
t22
t12
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ST10F166
AC Characteristics (Cont'd)
Figure 17. External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE
t5 ALE t16 t25
A17-A16 (A15-A8)
BHE
t17 Address t6 t7
t27
Read Cycle BUS Address t9
RD
t19 t18 Data In
t11
t15 t13
Write Cycle BUS Address t9
WR
t23 Data Out
t11
t22
t13
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ST10F166
AC Characteristics (Cont'd)
Figure 18. Ext. Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE
t5 ALE t16 t25
A17-A16 (A15-A8)
BHE
t17 Address t6 t7
t27
Read Cycle BUS Address
t19 t18 Data In
t9
RD
t11
t15 t13
Write Cycle BUS Address Data Out
t23
t9
WR
t11
t22
t13
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ST10F166
AC Characteristics (Cont'd)
Demultiplexed Bus for the ST10F166 VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)
Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay) Data float after RD rising edge (no RW-delay) Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR Symbol t5 CC t6 CC t8 CC t9 CC t12 CC t13 CC t14 SR t15 SR t16 SR t17 SR t18 SR t20 SR t21 SR t22 CC t24 CC t26 CC t28 CC Max. CPU Clock = 20 MHz min. 15 + tA 10 + tA 15 + tA -10 + tA 40 + tC 65 + tC - - - - 0 - - 35 + tC 15 + tF -10 + tF 0 + tF max. - - - - - - 30 + tC 55 + tC 55 + tA + tC 75 + 2t A + tC - 35 + tF 15 + tF - - - - Variable CPU Clock 1/2TCL = 1 to 20 MHz min. TCL - 10 + tA TCL - 15 + tA TCL - 10 + tA -10 + tA 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - - 2TCL - 15 + tC TCL - 10 + tF -10 + tF 0 + tF max. - - - - - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 25 + 2t A + tC - 2TCL - 15 + tF TCL - 10 + tF - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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ST10F166
AC Characteristics (Cont'd)
Demultiplexed Bus for the ST10F166-16 VSS = 0 V VCC = 5 V 10 %; TA = 0 to +70 C CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)
Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay) Data float after RD rising edge (no RW-delay) Data valid to WR Data hold after WR max. - - - - - - 47.5 + tC 72.5 + tC 72.5 + t A + tC 100 + 2t A + tC - 47.5 + tF 15 + tF - - - - Variable CPU Clock 1/CLP = 1 to 20 MHz min. TCLmin - 10 + tA TCLmin - 15 + tA TCLmin - 10 + tA -10 + tA CLP - 10 + tC CLP+TCLmin - 10 + tC - - - - 0 - - CLP - 15 + tC TCLmin - 10 + tF -10 + tF 0 + tF max. - - - - - - CLP - 20 + tC CLP+TCLmin - 20 + tC CLP+TCLmin - 20 + tA + t C 2CLP - 25 + 2tA + tC - CLP - 15 + tF TCLmin - 10 + tF - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t5 CC t6 CC t8 CC t9 CC t12 CC t13 CC t14 SR t15 SR
t16 SR t17 SR t18 SR t20 SR t21 SR t22 CC t24 CC
15 + tA 10 + tA 15 + tA -10 + tA 52.5 + t C 77.5 + t C - - - - 0 - - 47.5 + t C 15 + tF -10 + tF 0 + tF
ALE rising edge after RD, WR t26 CC Address hold after RD, WR t28 CC
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ST10F166
AC Characteristics (Cont'd)
Figure 19. Ext. Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE
t5 ALE t16 t26
A17-A16 A15-A0
BHE
t17 Address t6
t28
Read Cycle BUS (D15-D8) D7-D0 t8
RD
t20 t18 Data In
t14 t12
Write Cycle BUS (D15-D8) D7-D0 t8
WR
t24 Data Out
t22
t12
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ST10F166
AC Characteristics (Cont'd)
Figure 20. Ext. Mem. Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE
t5 ALE t16 t26
A17-A16 A15-A0
BHE
t17 Address t6
t28
Read Cycle BUS (D15-D8) D7-D0 t8
RD
t20 t18 Data In
t14 t12
Write Cycle BUS (D15-D8) D7-D0 t8
WR
t24 Data Out
t22
t12
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ST10F166
AC Characteristics (Cont'd)
Figure 21. Ext. Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE
t5 ALE t16 t26
A17-A16 A15-A0
BHE
t17 Address t6
t28
Read Cycle BUS (D15-D8) D7-D0 t9
RD
t21 t18 Data In
t15 t13
Write Cycle BUS (D15-D8) D7-D0 t9
WR
t24 Data Out
t22
t13
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ST10F166
AC Characteristics (Cont'd)
Figure 22. Ext. Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE
t5 ALE t16 t26
A17-A16 A15-A0
BHE
t17 Address t6
t28
Read Cycle BUS (D15-D8) D7-D0 t9
RD
t21 t18 Data In
t15 t13
Write Cycle BUS (D15-D8) D7-D0 t9
WR
t24 Data Out
t22
t13
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ST10F166
AC Characteristics (Cont'd)
CLKOUT and READY for ST10F166, VSS = 0 V VCC = 5 V 10 %; TA = 0 to +70 C CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2)
Notes:
1) 2)
Symbol t29 CC t30CC t31CC t32 CC t33 CC t34 CC t35 SR t36 SR t37 SR t58SR t59SR t60SR
Max. CPU Clock = 20 MHz min. 50 15 15 - - 0 + tA 10 10 65 20 0 0 max. 50 - - 5 5 10 + tA - - - - - 0 + 2t A + tF
2)
Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 2TCL TCL - 10 TCL - 10 - - 0 + tA 10 10 2TCL + 15 20 0 0 max. 2TCL - - 5 5 10 + t A - - - - - TCL - 25 + 2tA + t F
2)
Unit ns ns ns ns ns ns ns ns ns ns ns ns
These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY.
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ST10F166
AC Characteristics (Cont'd)
CLKOUT and READY for ST10F166-16 VSS = 0 V VCC = 5 V 10 %; TA = 0 to +70 C CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2)
Notes:
1) 2)
Symbol t29 CC t30CC t31CC t32 CC t33 CC t34 CC t35 SR t36 SR t37 SR t58SR t59SR t60SR
CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. 62.5 15 15 - - 0 + tA 10 10 77.5 20 0 0 max. 62.5 - - 5 5 10 + tA - - - - - 0 + 2t A + tF
2)
Variable CPU Clock 1/CLP = 1 to 20 MHz min. CLP TCLmin - 10 TCLmin - 10 - - 0 + tA 10 10 CLP + 15 20 0 0 max. CLP - - 5 5 10 + tA - - - - - TCL - 25 + 2tA + tF
2)
Unit ns ns ns ns ns ns ns ns ns ns ns ns
These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA refer to the next following bus cycle.
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ST10F166
AC Characteristics (Cont'd)
Figure 23. CLKOUT and READY
Running cycle 1) t32 t30 t34 ALE t31 t33 t29 READY waitstate MUX/Tristate 6)
CLKOUT
7)
Command RD, WR
2)
t35 Sync
READY
3)
t36
t35
3)
t36
t58 Async
READY
3)
t59
t58
3) 5)
t59
t60
4)
t37
see 6)
Notes:
1) 2) 3)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). The leading edge of the respective command depends on RW-delay. READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (eg. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note 4)). Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. The next external bus cycle may start here
4)
5)
6)
7)
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ST10F166
AC Characteristics (Cont'd)
External Bus Arbitration VSS = 0 V VCC = 5 V 10 %; TA = 0 to +70 C for ST10R165 CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
Parameter HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay Other signals release Other signals drive Symbol Max. CPU Clock = 20 MHz min. t61 SR t62 CC t63 CC t66CC t67CC 20 - - - -5 max. - 30 30 25 35 Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 20 - - - -5 max. - 30 30 25 35 ns ns ns ns ns Unit
Figure 24. External Bus Arbitration, Releasing the Bus
CLKOUT
t61
HOLD
t63
HLDA
1) t62
BREQ
2)
t66 Other Signals
1)
Notes:
1) 2)
The ST10R165 will complete the currently running bus cycle before granting bus access. This is the first possibility for BREQ to get active. 60/62
ST10F166
AC Characteristics (Cont'd)
Figure 25. External Bus Arbitration, (Regaining the Bus)
2)
CLKOUT
t61
HOLD
t62
HLDA
t62
BREQ
t62
1)
t63
t67 Other Signals
Notes:
1)
This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10R165 requesting the bus. The next ST10R165 driven bus cycle may start here.
2)
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ST10F166
19 GENERAL INFORMATION
Figure 26. Package Outline PQFP100 (14 x 20 mm)
mm Dim Min A A2 D D1 D3 E E1 E3 e 16.95 13.90 2.55 22.95 19.90 2.80 23.20 20.00 18.85 17.20 14.00 12.35 0.65 Number of Pins ND NE N 30 20 100 17.45 14.10 0.695 0.547 Typ Max 3.40 3.05 23.45 20.10 0.100 0.931 0.783 0.110 0.913 0.787 0.742 0.667 0.551 0.486 0.026 0.687 0.555 Min Typ Max 0.134 0.120 0.923 0.791 inches
Table 8. Ordering Information
Type ST10F166BQ1 PQFP-100 ST10F166BQ1-16 Package Function 16-bit microcontroller, 0 C to +70 C, 1 KByte RAM, 32 KByte Flash EPROM 16-bit microcontroller, 0 C to +70C, w/o Prescaler, 1 KByte RAM, 32 KByte Flash EPROM
Information furnished is believed to be accurate and reliable. However, SGS-TH OMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THO MSON Microelectronics. (c)1996 SGS-THOMSON Microelectronics -Printed in Italy - All Rights Reserved. SGS-THO MSON Microelectronics GROUP OF COMPANIE S Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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